5, longer on times mean greater DC switching losses, thus, reducing DC losses can be accomplished by reducing the on time/duty cycle of the FET. Also, DC losses are proportional to the percentage on time for the FET which is the duty cycle of the controller for the high side FET and 1 minus the duty cycle for the low side FET as was previously mentioned. The easiest way to reduce DC losses is to select a FET with low R DS(ON). So, to accurately determine the R DS(ON) an iterative process must be used which takes into account the temperature rise of the FET using Equations (3), (4) and (5). However, this is complicated by the fact that the R DS(ON) varies with the FET junction temperature. This is a fairly straightforward I 2R loss mechanism as shown in Fig. So, another way to lower AC losses is to lower the switching frequency, but this requires a larger and usually more expensive inductor to keep the peak switch current within specification.ДC losses occur when the switch is in the on state and are due to the R DS(ON) of the FET. Thus, higher frequency means greater AC switching loss. The higher the switching frequency, the greater the percentage of the switching period time is spent in the rise and fall transition regions as shown in Fig. Another factor is the switching frequency. This can be done by choosing a FET with lower gate charge. According to Equation (4), one way to reduce these losses is to reduce the rise and fall times of the switch. The AC switching losses occur during the transition between the switch being on and off, when the voltage and current through the switch are both non-zero.

Other loss mechanisms are due to output parasitic capacitance, gate losses, and body diode losses due to conduction during the dead time for the low side FET, but we will focus on the AC and DC losses in this discussion. T SW = Switching time period of controller (1/switching frequencyДC losses: P swDC = R DS(ON) * I OUT * I OUT * Duty cycle (5) The power dissipation can be broken down into two main areas, AC and DC losses.

This requires calculation of the power dissipation in the FETs. We can estimate the junction temperature of a FET using the Оё JA, or thermal resistance, of the package/heat sink, the power dissipated in the FET and the ambient temperature: The key issue is that the FETs may get too hot and burn up if the power dissipation is too high and the heat sinking is inadequate. Factors that need to be considered in FET selection are the voltage rating, ambient temperature, switching frequency, drive capability of the controller, and heat sink area. The disadvantage is that the FET selection process can be difficult since there are many factors to consider.ДЄ typical question is вЂњWhy wonвЂ™t this 10A FET work for my 10A Design?вЂќ The answer is that the 10A rating doesnвЂ™t necessarily apply to all designs.

This allows the greatest heat dissipation since it physically separates the FETs from the controller and it also gives the greatest flexibility in selecting the proper FETs for the job. But in order to provide high current capability and/or to achieve the highest efficiency, the FETs need to be kept external to the controller. The FETs may be integrated into the same chip as the controller, which provides the simplest solution.

The equations for duty cycle for a buck regulator are:Дuty Cycle (High side FET) = V OUT/(V IN Г— Efficiency) (1)Дuty Cycle (Low side FET) = 1 - DC (High side FET) (2) In this configuration, the FETs are switched on and off according to a duty cycle set by the controller in order to achieve the desired output voltage. An example of a step-down (or buck) synchronous switching regulator with a high side FET and a low side FET is shown in Fig. On-line design tools such as Texas InstrumentsвЂ™ WEBENCHВ® Power Architect can ease this process and allow the user to make decisions based on efficiency, footprint and cost to achieve desired design goals for MOSFET controller designs.ДC-to-DC switching power supplies are commonly used in modern day electronic systems for their high efficiency. This situation becomes more complicated within a multiple load power supply system. A balance between low gate charge and R DS(ON) must be achieved in order to keep the temperature of the MOSFET within specification. It is not sufficient to merely look at the voltage and current ratings for a MOSFET. MOSFET selection for DC-to-DC switching controllers can be a complicated process.

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